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TEST 2  -  U33 ROM CHECKSUM
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Step 1. Performs CPU test - halt on fail
Step 2. Verifies that 8 bit checksum of ROM is 00 - halt on fail  (part of code initialises the DMA page register)
Step 3. Displays "02" on the POST card then halts



Based on the 27OCT82 version of the BIOS chip, U33.
The following code was substitued at offset 00D3.

U33 appears at FE000 and so for example, offset 0123 will be address FE123 in the machine.

OFFSET CODE         
------------------------------------------------
00D3   BO 02   MOV AL,2
00D5   E6 80   OUT 80H,AL    ; send 02 to POST card
00D7   F4      HLT           ; halt
