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TEST 2B  -  TIMER 1 - PART 2 OF 2
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Step 1. Performs CPU test - halt on fail
Step 2. Verifies that 8 bit checksum of ROM is 00 - halt on fail  (part of code initialises the DMA page register)
Step 3. Timer 1 - verify that it functions okay
Step 4. Timer 1 - set it up to refresh memory
Step 5. Displays "2B" on the POST card then halts


Based on the 27OCT82 version of the BIOS chip, U33.
The following code was substitued at offset 012B.

U33 appears at FE000 and so for example, offset 0123 will be address FE123 in the machine.

OFFSET CODE         
------------------------------------------------
012B   BO 2B   MOV AL,2B
012D   E6 80   OUT 80H,AL    ; send 2B to POST card
012F   F4      HLT           ; halt
