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TEST 2A  -  TIMER 1 - PART 1 OF 2
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Step 1. Performs CPU test - halt on fail
Step 2. Verifies that 8 bit checksum of ROM is 00 - halt on fail  (part of code initialises the DMA page register)
Step 3. Verify that timer 1 functions okay
Step 4. Displays "2A" on the POST card then halts



Based on the 27OCT82 version of the BIOS chip, U33.
The following code was substitued at offset 0104.

U33 appears at FE000 and so for example, offset 0123 will be address FE123 in the machine.

OFFSET CODE         
------------------------------------------------
0104   BO 2A   MOV AL,2A
0106   E6 80   OUT 80H,AL    ; send 2A to POST card
0108   F4      HLT           ; halt
