
AST RESEARCH, INC.

PREMIUM 386C

Processor              80386DX
Processor Speed        20MHz
Chip Set               AST
Max. Onboard DRAM      None (16MB on 32-bit external memory card)
Cache                  None (64KB on 32-bit external memory card)
BIOS                   AST
Dimensions             330mm x 218mm
I/O Options            32-bit external memory card slot, parallel port,
                       serial ports (2), SMART expansion/16-bit ISA
                       expansion slots (3)
NPU Options            80287/80387

                                                                   [Image]

                                CONNECTIONS

  Purpose                 Location     Purpose                 Location

  32-bit external            J7        Front panel                P5
  memory card                          switches & LEDs

  SMART expansion or    S1, S2 & S3    Speaker                    P6
  16-bit ISA

  Serial port 2              P2        External battery           P8
  header

  Floppy drive               P3        Optional ROM (odd)        U89
  interface (A: and
  B:)

  Third floppy drive         P4        Optional ROM              U88
  interface                            (even)

[Image]

                                CONNECTIONS

  Purpose                  Location    Purpose                   Location

  Serial port 1              COM1      Parallel port              LPT1

  Serial port 2              COM2      Keyboard                   KYBD

                        USER CONFIGURABLE SETTINGS

                Function                     Jumper          Position

     Factory configured - do not alter        E1             closed

     Factory configured - do not alter        E2             closed

     Factory configured - do not alter        E3             closed

     Factory configured - do not alter        E4              open

     Factory configured - do not alter        E5             closed

     Factory configured - do not alter        E6              open

  Note:Jumper E6 may not appear on all board revisions.

[Image]

                        USER CONFIGURABLE SETTINGS

               Function                     Switch           Position

     Parity check enabled               SW1/switch 7         closed

      Parity check disabled              SW1/switch 7          open

                            DRAM CONFIGURATION

     Size         Bank 0         Bank 1         Bank 2         Bank 3

    1MB 1      (4) 256K x 9       NONE           NONE           NONE

    2MB 1      (4) 256K x 9   (4) 256K x 9       NONE           NONE

    3MB 1      (4) 256K x 9   (4) 256K x 9   (4) 256K x 9       NONE

    4MB 1      (4) 256K x 9   (4) 256K x 9   (4) 256K x 9   (4) 256K x 9

    4MB 2       (4) 1M x 9        NONE           NONE           NONE

    5MB 1      (4) 256K x 9    (4) 1M x 9        NONE           NONE

    6MB 1      (4) 256K x 9   (4) 256K x 9    (4) 1M x 9        NONE

    7MB 1      (4) 256K x 9   (4) 256K x 9   (4) 256K x 9    (4) 1M x 9

    8MB 2       (4) 1M x 9     (4) 1M x 9        NONE           NONE

    9MB 1      (4) 256K x 9    (4) 1M x 9     (4) 1M x 9        NONE

    10MB 1     (4) 256K x 9   (4) 256K x 9    (4) 1M x 9     (4) 1M x 9

    12MB 2      (4) 1M x 9     (4) 1M x 9     (4) 1M x 9        NONE

    13MB 1     (4) 256K x 9    (4) 1M x 9     (4) 1M x 9     (4) 1M x 9

    16MB 2      (4) 1M x 9     (4) 1M x 9     (4) 1M x 9     (4) 1M x 9

  Notes 1 & 2 :Please see the next table for the proper switch settings
  for this configuration.

                          DRAM SWITCH CONFIGURATION

  Size   SW1/1   SW1/2    SW1/3    SW1/4    SW1/5    SW1/6    SW1/7    SW1/8

  1MB    open     open     open     open     open    open     closed   open
   1

  2MB    open    closed    open     open     open    open     closed   open
   1

  3MB    open    closed    open    closed    open    open     closed   open
   1

  4MB    open    closed    open    closed    open    closed   closed   open
   1

  4MB    open     open     open    closed    open    closed   closed   closed
   2

  5MB    closed   open     open     open     open    open     closed   open
   1

  6MB    open    closed   closed    open     open    open     closed   open
   1

  7MB    open    closed    open    closed   closed   open     closed   open
   1

  8MB    closed   open     open     open     open    open     closed   closed
   2

  9MB    closed   open    closed    open     open    open     closed   open
   1

  10MB   open    closed   closed    open    closed   open     closed   open
   1

  12MB   closed   open    closed    open     open    open     closed   closed
   2

  13MB   closed   open    closed    open    closed   open     closed   open
   1

  16MB   closed   open    closed    open    closed   open     closed   closed
   2

  Notes 1 & 2 :Please see the previous table for the proper configuration for
  these switch settings.

                            SRAM CONFIGURATION

          Size                              Cache SRAM

          64KB              (8) 8K x 8 on a SIMM-type module (AST Part#
                                            202303-001)

