
SPRITE, INC.

SM 386F (version 1.0)

Processor         80386DX
Processor Speed   33/40MHz
Chip Set          Forex
Max. Onboard DRAM 32MB
SRAM Cache        32/64/128KB
BIOS              AMI/MR
Dimensions        330mm x 218mm
I/O Options       None
NPU Options       80387/3167

[Image]

                                CONNECTIONS

  Purpose                   Location   Purpose                   Location

  External battery            JP2      Power LED & keylock         JP9

  Turbo LED                   JP7      Speaker                    JP10

  Reset switch                JP8      Turbo switch               JP11

                        USER CONFIGURABLE SETTINGS

                 Function                     Jumper         Position

     Monitor type select color                JP3            closed

      Monitor type select monochrome           JP3             open

     NPU mode select synchronous with         JP5           pins 1 & 2
      CPU                                                     closed

      NPU mode select asynchronous with        JP5           pins 2 & 3
      CPU                                                     closed

     External battery select 3.6VDC          JP200           closed

      External battery select 6.0VDC          JP200            open

     Battery select internal                 JP201           closed

      Battery select external                 JP201            open

     CMOS memory normal operation            JP202            open

      CMOS memory clear                       JP202           closed

              DRAM CONFIGURATION

      Size          Bank 0          Bank 1

      1MB         (4) 256K x 9       NONE

      2MB         (4) 256K x 9   (4) 256K x 9

      4MB         (4) 1M x 9         NONE

      5MB         (4) 256K x 9    (4) 1M x 9

      8MB         (4) 1M x 9      (4) 1M x 9

      16MB        (4) 4M x 9         NONE

      17MB        (4) 256K x 9    (4) 4M x 9

      20MB        (4) 1M x 9      (4) 4M x 9

      32MB        (4) 4M x 9      (4) 4M x 9

                            SRAM CONFIGURATION

   Size       Cache      Location     TAG (U15)   TAG (U16)       JP6
              SRAM

   32KB      (4) 8K x     Bank 0        NONE       (1) 8K x    pins 1 & 2
                8                                     8         closed

   64KB      (8) 8K x   Banks 0 & 1    (1) 8K x    (1) 8K x    pins 2 & 3
                8                         8           8         closed

   128KB     (4) 32K      Bank 0      (1) 32K x     NONE       pins 2 & 3
               x 8                        8                     closed

