
MICROMATION TECHNOLOGY, INC.

80386-WBH

Processor         80386DX
Processor Speed   33/40MHz
Chip Set          OPTI
Max. Onboard DRAM 32MB
SRAM Cache        32/64/128/256KB
BIOS              AMI
Dimensions        330mm x 218mm
I/O Options       None
NPU Options       80387/3167

[Image]

                                CONNECTIONS

  Purpose                   Location    Purpose                  Location

  External battery            J10       Turbo LED                  JP4

  Power LED & keylock         J23       Reset switch              JP11

  Speaker                     J24       Turbo switch               SW2

                        USER CONFIGURABLE SETTINGS

                Function                     Jumper          Position

     Monitor type select color                JP1            closed

      Monitor type select monochrome           JP1             open

     CMOS memory normal operation             JP2           pins 2 & 3
                                                              closed

      CMOS memory clear                        JP2           pins 1 & 2
                                                              closed

     I/O bus speed select CPU/6               JP3             open

      I/O bus speed select CPU/8               JP3            closed

              DRAM CONFIGURATION

      Size          Bank 0          Bank 1

      1MB         (4) 256K x 9       NONE

      2MB         (4) 256K x 9   (4) 256K x 9

      4MB         (4) 1M x 9         NONE

      5MB         (4) 1M x 9     (4) 256K x 9

      8MB         (4) 1M x 9      (4) 1M x 9

      16MB        (4) 4M x 9         NONE

      20MB        (4) 1M x 9      (4) 4M x 9

      20MB        (4) 4M x 9      (4) 1M x 9

      32MB        (4) 4M x 9      (4) 4M x 9

                         SRAM JUMPER CONFIGURATION

    Size         JP5         JP7          JP8          JP9        JP10

    32KB       pins 1 &    pins 1 &      open        pins 1 &    pins 2 &
                  2           2                         2           3

    64KB       pins 2 &    pins 1 &      open        pins 1 &    pins 1 &
                  3           2                         2           2

    128KB      pins 2 &    pins 2 &     closed       pins 1 &    pins 1 &
                  3           3                         2           2

    256KB      pins 2 &    pins 2 &     closed       pins 2 &    pins 1 &
                  3           3                         3           2

  Note:Pins designated should be in the closed position.

                    SRAM CONFIGURATION

     Size        Cache SRAM      Location         TAG

     32KB        (4) 8K x 8       Bank 0      (1) 8K x 8

     64KB        (8) 8K x 8    Banks 0 & 1    (1) 8K x 8

     128KB      (4) 32K x 8       Bank 0      (1) 32K x 8

     256KB      (8) 32K x 8    Banks 0 & 1    (1) 32K x 8

