
SILICON STAR INTERNATIONAL, INC.

FA4 MAIN BOARD

Processor         80386DX/CX486DLC
Processor Speed   33/40MHz
Chip Set          ALI
Max. Onboard DRAM 32MB
SRAM Cache        32/64/128/256KB
BIOS              AMI
Dimensions        240mm x 220mm
I/O Options       None
NPU Options       CX83D87

[Image]

                                CONNECTIONS

  Purpose                Location      Purpose                Location

  External battery          J4         Turbo switch         J7 pins 1 & 2

  Reset switch              J5         Turbo LED            J7 pins 4 & 5

  Speaker                   J6         Power LED &               J8
                                       keylock

                        USER CONFIGURABLE SETTINGS

                Function                     Jumper          Position

     Monitor type select color                JP1           pins 2 & 3
                                                              closed

      Monitor type select monochrome           JP1           pins 1 & 2
                                                              closed

     Factory configured - do not alter        JP2           pins 2 & 3
                                                              closed

     Factory configured - do not alter        JP7           pins 1 & 2
                                                              closed

     Factory configured - do not alter        JP8           pins 2 & 3
                                                              closed

           DRAM CONFIGURATION

  Size       Bank 0          Bank 1

  1MB     (4) 256K x 9        NONE

  2MB     (4) 256K x 9    (4) 256K x 9

  4MB      (4) 1M x 9         NONE

  8MB      (4) 1M x 9      (4) 1M x 9

  16MB     (4) 4M x 9         NONE

  32MB     (4) 4M x 9      (4) 4M x 9

                         SRAM JUMPER CONFIGURATION

    Size               Jumper JP5                     Jumper JP6

    32KB                  open                     pins 2 & 3 closed

    64KB                  open                     pins 1 & 2 closed

    128KB      pins 1 & 2, 3 & 4 and 5 & 6         pins 2 & 3 closed
                         closed

    256KB      pins 1 & 2, 3 & 4 and 5 & 6         pins 1 & 2 closed
                         closed

                    SRAM CONFIGURATION

     Size        Cache SRAM      Location         TAG

     32KB        (4) 8K x 8       Bank 0      (1) 8K x 8

     64KB        (8) 8K x 8    Banks 0 & 1    (1) 8K x 8

     128KB      (4) 32K x 8       Bank 0      (1) 32K x 8

     256KB      (8) 32K x 8    Banks 0 & 1    (1) 32K x 8

