
SILICON STAR INTERNATIONAL, INC.

VL-BUS 486 MAIN BOARD

Processor        80486SX/80487SX/80486DX/80486DX2
Processor Speed  25/33/40/50(internal)/50/66(internal)MHz
Chip Set         UNI
Max. Onboard DRAM32MB
Cache            64/128/256KB
BIOS             AMI/Award
Dimensions       330mm x 218mm
I/O Options      32-bit VESA local bus slots (2)

[Image]

                                CONNECTIONS

  Purpose                  Location    Purpose                  Location

  Power LED & keylock        CN1       External battery           CN6

  Speaker                    CN3       Reset switch               CN8

  Turbo LED                  CN4       Power LED                  LED1

  Turbo switch               CN5       32-bit VESA local bus    S1 & S2
                                       slots

                        USER CONFIGURABLE SETTINGS

                Function                     Jumper          Position

     CMOS memory normal                      JP12          pins 1 & 2
                                                              closed

      CMOS memory clear                       JP12          pins 2 & 3
                                                              closed

     FAST A20 enabled                        JP17          pins 1 & 2
                                                              closed

      FAST A20 disabled                       JP17          pins 2 & 3
                                                              closed

     Monitor type select color               JP18            Closed

      Monitor type select monochrome          JP18             Open

     Factory configured - do not             JP23          pins 1 & 2
      alter                                                   closed

     Factory configured - do not             JP24          pins 1 & 2
      alter                                                   closed

     Factory configured - do not             JP25          pins 1 & 2
      alter                                                   closed

     Factory configured - do not             JP26          pins 2 & 3
      alter                                                   closed

     Power good signal detect from           JP27          pins 2 & 3
      power supply                                            closed

      Power good signal detect from           JP27          pins 1 & 2
      board                                                   closed

     Factory configured - do not             JP28          pins 2 & 3
      alter                                                   closed

              DRAM CONFIGURATION

      Size          Bank 0          Bank 1

      1MB         (4) 256K x 9       NONE

      2MB         (4) 256K x 9   (4) 256K x 9

      4MB         (4) 1M x 9         NONE

      8MB         (4) 1M x 9      (4) 1M x 9

      16MB        (4) 4M x 9         NONE

      32MB        (4) 4M x 9      (4) 4M x 9

                            CACHE CONFIGURATION

    Size       Bank 0     Bank 1        TAG write         TAG write back
                                       through U15           U14,U15

    64KB      (4) 8K x    (4) 8K x       8K x 8            (2) 8K x 8
                 8           8

   128KB       (4) 32K     NONE          8K x 8            (2) 8K x 8
                x 8

   256KB       (4) 32K    (4) 32K        32K x 8           (2) 32K x 8
                x 8         x 8

                        CACHE JUMPER CONFIGURATION

      Size        JP1     JP2      JP3     JP4     JP5     JP6      JP7

   64KB write     N/A     N/A     1 & 2   1 & 2    2 & 3   1 & 2   1 & 2
    through

   64KB write     1 & 2   1 & 2   1 & 2   1 & 2    2 & 3   1 & 2   1 & 2
      back

   128KB write    N/A     N/A     2 & 3   1 & 2    1 & 2   1 & 2   2 & 3
    through

   128KB write    2 & 3   1 & 2   2 & 3   1 & 2    1 & 2   1 & 2   2 & 3
      back

   256KB write    N/A     N/A     2 & 3   2 & 3    2 & 3   2 & 3   2 & 3
    through

   256KB write    2 & 3   2 & 3   2 & 3   2 & 3    2 & 3   2 & 3   2 & 3
      back

  Note:Pins designated should be in the closed position.

         CPU SPEED CONFIGURATION

   Speed      JP20      JP21      JP22

   25MHz     Closed     Open     Closed

   33MHz      Open     Closed    Closed

   40MHz     Closed     Open      Open

  50iMHz     Closed     Open     Closed

   50MHz      Open     Closed     Open

  66iMHz      Open     Closed    Closed

                          CPU TYPE CONFIGURATION

    CPU Type         JP13           JP14           JP15          JP16

  80486SX PGA        open         pins 2 & 3       Open         Closed
                                   closed

  80486 SX PQFP      open         pins 2 & 3       Open          Open
                                   closed

    80487SX        pins 2 & 3     pins 1 & 2      Closed          N/A
                    closed         closed

  80486DX, DX2     pins 1 & 2     pins 1 & 2      Closed          N/A
                    closed         closed

                  VESA WAIT STATE/BUS SPEED CONFIGURATION

  CPU speed     Wait states     JP8         JP9        JP10       JP11

   < 33MHz        0 wait      pins 1 &    pins 1 &   pins 1 &    pins 1 &
                  states         2           2          2           2

   > 33MHz        1 wait      pins 2 &    pins 2 &   pins 2 &    pins 2 &
                  state          3           3          3           3

  Note: Pins designated should be in the closed position.

