

                           IDE Plus CONTROLLER - VL
                           ------------------------

This file contains additional installation details; the latest additions
to the manual; and technical specifications for getting the best performance
from your IDE Plus Controller - VL (Product Code IDEVL2).

    This file contains 2 sections:


                                Section one
                                -----------

           I............................... Software Installation Details.
          II..................................Motherboard Speed Selection.
         III...............................  The use of VL-bus wait-state.
          IV............................   Logical Block Addressing (LBA).
           V..................................Obtaining Technical Support.


                                Section two
                                -----------

           I...............................Multiple Sector Transfer (MST).
          II.......32-bit Operation by Device Driver or Extended ROM BIOS.
         III.......................................IDE Drive Cycle Timing.
          IV...........................Motherboard BIOS vs. Device Driver.
           V........Data Transfer Cycle:  Concurrent Read/Write Operation.
          VI......What Affects IDE Drive Performance (Data Transfer Rate).
         VII.........................How To Make a Performance Comparison.
        VIII.............................................Seek Performance.



                                Section one
               Detailed Installation Guidelines for the IDEVL2
               ===============================================

I.   Software Installation Details.

     The INSTALL utility on the distribution diskette makes the following
     installations for you. The following instructions are for users who
     wish to manually install the software drivers.

     A. DOS Device Driver Installation

        2015PL.SYS is the DOS device driver supplied with the IDEVL2. Add the
        following line to the very beginning of you CONFIG.SYS file.

           Device=C:\IDEVL2\2015PL.SYS

        You may place 2015PL.SYS  in one of your sub-directories, but make
        sure that the proper directory path is specified in the DEVICE= command
        line.

        The DOS device driver replaces the ROM-BIOS routines on your PC's
        system board with routines that can take advantage of the capabilities
        of the IDEVL2 controller.


    B.  Microsoft Windows Driver Installation

        Microsoft Windows version 3.1 supports 32-bit disk access, but the
        disk data transfer between host and the IDE adapter is still limited
        by the 16-bit ISA bus. If you want to speed up your hard drives under
        Windows through the 32-bit VL-Bus, you will need to modify the
        SYSTEM.INI in your Windows SYSTEM directory (this file primarily
        contains settings that customize Windows to meet your system's
        hardware needs).  If you do not modify the SYSTEM.INI file, your system
        will still function, but performance will not be optimized.

        Please follow the following steps to modify your SYSTEM.INI file:

        1. Use any ASCII word processor to open your SYSTEM.INI file.
           Search the [386 Enh] section to find the following lines:

              [386Enh]
              device=*int13
              32BitDiskAccess=on
              device=*wdctrl

        2. If the statement "32BitDiskAccess=Off", change it to "ON".

        3. Insert a ";" before the line "device=*wdctrl" to disable the
           wdctrl setting, so the previous lines should be:

              [386Enh]
              device=*int13
              32BitDiskAccess=on
              ;device=*wdctrl

        4. Add the following line to the [386Enh] Section

              device=C:\windows\system\2015P.386

           You may place 2015P.386 in any one of your sub-directories, but
           make sure that the proper directory path is specified in the
           statement you add to the 386Enh section


           The lines above should now read:

              [386Enh]
              device=*int13
              32BitDiskAccess=on
              ;device=*wdctrl
              device=C:\windows\system\2015P.386

         5. Save the new SYSTEM.INI file.

         6. Copy the file 2015P.386 to the directory you specified in step 4,
            usually C:\windows\system

         7. Load or restart Windows to bring up your PC with the new system
            configuration.

II.  Motherboard Speed Selection

     The 2015P driver will attempt to program the IDEVL2
     to the best speed setting for each drive.  But it does this while
     making the assumption that the motherboard is running at 50MHz.  If
     the 2015P is being used on a 33MHz motherboard, some drives may get
     better results using the 33MHz timing tables.

     If the 2015P is running on a 33MHz motherboard, then you can
     tell the IDEVL2 to use the 33MHz timing table by adding the
     following switch to the "device=" line in the CONFIG.SYS file:

         DEVICE=C:\IDEVL2\2015PL.SYS /P:33

     The "/P:33" option tells the device driver to use the 33MHz timing
     table instead of the default 50MHz timing table.




III  The use of VL-bus wait-state.
     The IDEVL2 does not function well with a VL-bus wait-state inserted
     in the timing clock.

     Some motherboard vendors call this option "VL-bus Wait State" or
     "Local Bus Ready". This option should be set to "Disabled" or "Bypass"


IV   Logical Block Addressing (LBA)
     The IDEVL2 does not currently support LBA. If you have LBA options
     in your system BIOS, then it must be disabled.


V    Obtaining Technical Support


    If  you  need  technical  support  for  your  Boca  Research
    Product, You should first contact your dealer. The Dealer is
    most familiar with your system and is  the  primary  contact
    for  technical  questions. In addition, Boca Research offers
    several levels of technical support:


    1.  For immediate access to a highly trained technician, our
    priority  support  service  can  be   reached   by   dialing
    1-900-555-4900  between  the  hours of 8 AM and 8 PM Eastern
    Time, Monday through Friday. The charge for this call is  $2
    per minute.

    2.   Our  QuickFax  service  contains  product  information,
    technical  specifications,  and  helpful installation hints.
    From  the  phone   attached  to  your  fax   machine,   dial
    407-995-9456 24 hours a day and follow the voice prompts.

    3.   Our Bulletin Board Service is also available 24 hours a
    day at 407-241-1601. The latest  drivers  and  software  are
    available  here,  as  well  as  technical  hints and product
    information.

    4.  If you subscribe to CompuServe, you can "GO  BOCA"  to
    access the latest drivers and software for our products.

    5.   For  direct  questions  about  specific  products,  our
    technical  support department can be reached at 407-241-8088
    between the hours of 8 AM and 6:30 PM Eastern  Time,  Monday
    through Friday. Please have your computer case open with the
    product installed when you call.




                            Section Two
               Technical Specifications of the IDEVL2
             ===============================================

The following outline discusses the issues most commonly faced
when dealing with how the IDEVL2 integrates into the architecture
of the VESA local bus to IDE hard drive interface.


I.   Multiple Sector Transfer (MST).

     The conventional AT BIOS handles hard drive data in a 512
     byte cluster called a sector.  Each time the system
     transfers a sector to or from the hard drive, some time is
     spent establishing and finishing the transfer.  These
     operations can be grouped together and considered as the
     "transfer overhead".  This transfer overhead remains the
     same regardless of the size of the sector.  During our
     testing, we have found that in many systems this overhead
     takes about the same time as the actual data transfer.
     Thus, eliminating the transfer overhead would nearly double
     the transfer rate.

     The ANSI ATA standard supports "Multiple Sector Transfers"
     (MST).  This groups a number of sectors together into one
     package.  This package can then be transferred using a single
     "transfer overhead".  If a drive is capable of transferring
     64 sectors in one MST package, then the transfer overhead
     would be one-sixty-fourth of what it would be if each sector
     were to be transferred individually.

     Some final notes that are important to keep in mind:

     1.   Not all IDE drives support MST.

     2.   Not all IDE drives that support MST can do it very
          efficiently.

     3.   The BIOS on current motherboards does not support MST.

     4.   MST factors of 2,4,8,16,32 and 64 are defined by the
          ANSI ATA standard.



II.  32-bit Operation by Device Driver or Extended ROM BIOS.

     Currently, IDE drives have a 16-bit interface for data
     transfers and an 8-bit interface for programmed I/O.  Also,
     the motherboard BIOS supports only 16-bit IDE routines.  To
     take advantage of the VESA 32-bit bus, a 32-bit instruction
     based hard drive routine can replace the motherboard's
     original 16-bit instruction based BIOS routine.

     The IDEVL2 interface chip provides the interface between the
     32-bit local bus and the 16-bit IDE drive, by automatically
     translating a 32-bit local bus cycle into two consecutive
     16-bit IDE cycles with a minimum of overhead on both the
     VESA and IDE sides.

     Usually, it will take a device driver or an extended ROM
     BIOS to replace the motherboard BIOS IDE routine to realize
     the 32-bit access. The 2015PL.SYS driver does this when
     it is loaded in your config.sys file.


III. IDE Drive Cycle Timing.

     The ANSI ATA revision 3.0 specifies three types of IDE cycle
     timing as described in the following table.  Each drive
     manufacturer tries to minimize the data transfer timing in
     order to provide a faster transfer.  Different IDE drives
     will come with their own timing specifications which are at
     least the same or faster than the timing defined by one of
     the 3 IDE timing types.

     In theory, an IDE drive with a 300ns cycle time is faster
     than an IDE drive with 400ns cycle time.  However, on the
     ISA bus, there is very little we can do to improve the IDE
     cycle timing since the ISA bus is running at a very low
     speed to insure compatibility with the slowest type of IDE
     timing.  Some motherboards offer a more efficient ISA cycle
     that can actually run at a faster IDE cycle timing than
     other motherboards, but the improvement is limited.

     However, on a VL-bus, we can tailor the IDE timing to the
     individual IDE specification and actually take advantage of
     the faster IDE data transfer timing offered by aggressive
     IDE drive manufacturers.


     Table of IDE Cycle Timing, ANSI ATA revision 3.0:
     
              +----------------------+----------------------+
              | 16-bit Data Transfer | 8-bit Programmed I/O |
     +-------------------------------+----------------------+
     | Drive  |  Active	   Cycle     |	Active	  Cycle     |
     | Type   |  pulse	    time     |	pulse	   time     |
     +--------+----------------------+----------------------+
     | Type 2 |   100       240      |   290      >290      |
     | Type 1 |   125       383      |   290       383      |
     | Type 0 |   165       600      |   290       600      |
     +--------+----------------------+----------------------+



IV.  Motherboard BIOS vs. Device Driver.

     The original motherboard BIOS's were developed to work with
     all existing IDE drives, so they tended to have very
     conservative timing and thus had very slow access times.
     The latest versions have improved the IDE data transfer
     efficiency, but are still limited to 16-bit ISA bus
     operation and, as mentioned earlier, they do not support
     MST.

     Since the motherboard BIOS works together with the
     motherboard chipset, different combinations of
     BIOS/chipset's produce different IDE data transfer
     performances.  In other words, the same drive/controller
     will produce different results on different motherboards.

     To overcome these limitations, the motherboard's IDE BIOS
     routines are replaced with the 2015PL.SYS routines when the
     2015PL.SYS driver is loaded.

     In summary, the reasons for replace the BIOS routines are as
     follows:
     
     1.   Provide more efficient 32-bit transfer routines.

     2.   To enable MST operation, if the IDE drive supports it.

     3.   Identify the IDE drive in use to select the fastest
          possible IDE data transfer cycle timing.
     


V.   Data Transfer Cycle:  Concurrent Read/Write Operation.

     To read a block of data, the CPU must transfer it 32 bits at
     a time.  For the typical 512 byte sector, this means cycling
     through a transfer loop 128 times.  If a block (one or more
     sectors) is to be read from the IDE drive buffer into
     memory, then the transfer consists of an I/O read from the
     drive buffer, followed by a memory write.  To write a block
     from memory to the drive buffer, the sequence is just
     reversed:  a memory read followed by an I/O write.

     During a read cycle, the IDEVL2 fetches the 32-bit chunk of
     DATA from the IDE drive buffer and presents it to the CPU
     through the I/O channel.  Then the CPU writes the data to
     the main memory.  The functions are just reversed during a
     WRITE Cycle.

     Since the IDEVL2 is running on the local CPU bus, the timing
     between the IDEVL2 and the CPU is so closely tied as to appear
     to be synchronous.  Because of this synchronous timing, the
     IDEVL2 does not have to wait for the CPU to finish writing the
     DATA to memory before the IDEVL2 retrieves the next 32-bit
     chunk of data.  Thus, this transfer can be said to be
     concurrent.  That is, while the CPU is reading or writing
     memory, the IDEVL2 is loading or unloading the IDE drive
     catch.  This parallel operation technique reduces the
     transfer time.


VI.  What Affects IDE Drive Performance (Data Transfer Rate)

     1.   The IDE Hard Drive Routines.

          As discussed in Section IV, the motherboard BIOS
          routines are not sophisticated enough to take advantage
          of the newer high-performance IDE drives.  Replacing
          these low-end routines with higher performance routines
          results in significant transfer rate improvements.  The
          IDEVL2 is packaged with a Device Driver or a ROM BIOS
          that takes advantage of these high performance drive
          features.

     2.   Multiple Sector Transfer (MST) Factor.

          As discussed in Section I, a communication link (hand-
          shaking) must be established each time data needs to be
          transferred.  The larger the data package, the less time
          spent hand-shaking, and the more time spent working.
          Thus, the larger the MST factor, the better the data
          transfer rate.

          The size of the drive's data buffer as well as the
          drive's internal controller algorithm will determine
          the MST factor.

     3.   The IDE Drive Access Time.

          The Access Time is the delay between the time data is
          requested, and the drive says that it has the data
          ready.  From the perspective of the IDEVL2, the hard
          drive is considered a 'black box'.  This means that it
          is not known what the drive does to get the data that
          is requested.   The IDEVL2 just deals with the drive's
          DATA buffer.	This data buffer is the window through
          which all data is transferred.  The IDEVL2 requests the
          DATA from the drive and at some time later the drive
          says that it has the data ready in the buffer.  This
          delay is called the Access Time of the drive.

     4.   The Data Transfer Cycle Time.

          The Data Transfer Time counts how long it takes to move
          one 32-bit chunk of data from the IDE drive buffer to
          the CPU and then to the main memory.  This process must
          cycle through 128 times to transfer one 512 Byte
          sector.  There are two distinct concerns for
          performance AS follows:


          A.   The IDE Drive Data Transfer Cycle.
     
               The electrical characteristics of the drive's data
               buffer will determine the fastest possible speed
               at which the data can be transferred to or from the
               buffer to the I/O bus.
     
          B.   The Motherboard Local Bus Cycle Efficiency.
     
               There are two factors that determine how long the
               motherboard takes to complete its' side of the
               DATA transfer.

                  i.  The motherboard chipset design will determine
                         how efficiently the local bus transfer is
                         handled.       Some motherboards introduce some
                         timing overhead to provide more tolerance.

                  ii. The wait states imposed on main memory access
                         will determine how long it takes to complete
                         the memory read or write.

     Usually these factors combine to produce a Data Transfer
     Cycle Time that is faster than most IDE drives.  But on some
     systems, an unusually high number of DRAM wait states and an
     inefficient chipset design can create an environment in
     which the IDEVL2 will need to be run at a slower than normal
     speed setting.


VII. How To Make a Performance Comparison.

     In general, using the same motherboard, drive and testing
     program, you should get a consistent performance grading:
     The IDEVL2 with Driver will be the fastest; The IDEVL2 using
     the generic motherboard IDE BIOS routines will be second;
     And the ISA IDE IO card with the motherboard IDE BIOS
     routines is the slowest.

     In rare cases one may see little or no difference.  This is
     due to a variety of factors relating to the hard drive as
     discussed in Sections VI.2, VI.3 and VI.4.A.
     Essentially, the IDE drive itself is the bottleneck, not the
     bus.  Keep in mind the 'black box' idea:  the drive
     controller does not have any control over how the IDE drive
     stores or retrieves that data.  The IDEVL2 deals only with the
     IDE drive buffer, the window through which all of the data
     must pass.

     A final point on this subject, the purpose of the IDEVL2 is to
     take advantage of the latest high performance IDE drives.
     If no improvement is seen, then the drive being used does
     not use any of the latest high performance features.


VIII.  Seek Performance.

     Some performance rating programs will conduct a "Seek
     Performance Test" to see how fast the drive seeks a
     particular sector.  This is essentially testing the Access
     Time of the drive as discussed in Section VII.3.  This type
     of test is usually one of several tests run to gage the
     over-all performance of the drive.

     The seek operation is important for non-IDE hard drives
     because the hard drive controller must first seek the
     targeted sector before the transfer can be started.  With
     an IDE drive, all that is needed is a request for a
     particular sector;  The intelligent controller built onto
     the drive takes care of seeking and retrieving the sector
     and thus a seek command is not necessary for normal IDE hard
     drive operation.

     The Device Driver for the IDEVL2 processes a seek command by
     verifying with the drive controller that the sector is
     valid, and then it immediately reports back that the seek is
     done.  No access time is actually involved and thus the seek
     time is essentially zero.

     We have noticed that this 'zero seek time' creates a problem
     with the Norton hard drive performance utility.  Norton
     makes the assumption that the seek operation will take at
     least a certain minimum time.  Because of this assumption,
     it ignores the immediately received 'seek done' status,
     thinking that the status must be invalid.  At some point
     later it decides that the status must be valid, notes the
     time (absurdly long) and thus ends up giving erroneous
     results.


                               ----*----


