PCI.EXE version 0.7 by John S. Fine <johnfine@erols.com>

   This program is for viewing or changing registers in PCI
configuration space.

   Use this program entirely at your own risk.  I make no claim that
this program is suitable or safe for any purpose.

ZER0-PRICE SHAREWARE:

   If you continue to use this program after a reasonable initial test,
you must register it.  You do not need to send any money.  Registration
consists entirely of sending an EMAIL to johnfine@erols.com to tell me
that you are using it, and where you got your copy.  Bug reports and
suggestions are also welcome, though I can't promise to do anything
with them.

USAGE:

   To display all information that the program can decode from PCI
devices on your system, simply type "PCI | MORE".

   For some PCI chipsets it will decode many of the settings, so it can
be used to check BIOS settings for DRAM timing etc. if you have a BIOS
that does not show you all the settings for your chipset.

   If you have documentation on the configuration registers for any PCI
device, you can use PCI.EXE to write the registers and select options
that your BIOS or PnP drivers don't make available.  In most cases this
can be done only in hexidecimal form, so you need to know what you are
doing.  In a few cases, I built in slightly more meaningful switches to
control certain features, and you can determine the correct command with
just this documentation.

   Often you will get minimum information such as the example below.  I
don't have any register documentation for this device, so I couldn't
program any details.

--------------------------------------------------
| PCI bus: 0  device: 12  function: 0		 |
| Vendor:          1013  Cirrus Logic		 |
| Device:          00A0  GD 5340 GUI Accelerator |
| Revision:        45				 |
| Class:           3.0				 |
--------------------------------------------------

   On some devices you get more detail, such as the example below:

---------------------------------------------------------------------------
| PCI bus: 0  device: 00  function 0					  |
| Vendor:          8086  Intel Corporation				  |
| Device:          122D  82437FX: System controller			  |
| Revision:        2							  |
| Class:           6.0							  |
| L2 Cache:        Pipelined Burst 256Kb				  |
| Refrsh based on: 66 MHz  {50-66}					  |
| DRAM timing:     Read:7333, EDO read:7222, Write:5222, RAS/CAS:2, Pre:3 |
|                  {7333-8444} {7222-8444}   {5222-6444}   {2-3}    {3-4} |
| C0000-C7FFF:     Read Cache						  |
| C8000-EFFFF:    							  |
| F0000-FFFFF:     Read Cache						  |
| Bank 1:          8Mb EDO						  |
| Bank 3:          8Mb EDO						  |
| SMM:             Enabled						  |
---------------------------------------------------------------------------

   I did my best to make the descriptions short but meaningful.  In many
cases I didn't succeed.  For example, the "Pre:3".  If you know how
precharge time affects your memory performance then you know more about
it than I do, and you don't need a better description.  If you don't
know, then the best description I could give wouldn't help a lot.

   I also did my best to make the information accurate, but there are
many details I may have misunderstood.  If my program says your EDO read
cycles are 7222 when your BIOS or motherboard manual says they are 5222,
don't dash back to the store for repair or refund.  Check further before
trusting any unexpected output from my program.  If you do spot an
error, please EMAIL me about it.

   The description of memory banks may be a little confusing.  The
system on which I produced the above example has two 8Mb SIMMs, both of
which are in what the motherboard manual calls "bank 0".  PCI.EXE
numbers banks based on how they are wired to the DRAM controller.  The
bank numbers in the motherboard manual may not correspond.

   Also, reporting two 8Mb SIMMs as two 8Mb banks (rather than one 16Mb
bank) is correct, but it does NOT mean that each SIMM is a bank.  Each
SIMM may be one or two "half-banks".  Even though an 8Mb SIMM is usually
two 4Mb half-banks, it does not add up to a whole bank.  Two half banks
only form a whole bank when they are in paired SIMM sockets.  Thus, the
two 8Mb banks in the above example each consist of half of one SIMM
combined with half of the other.

-------------------------------------------------------------
| PCI bus: 0  device: 07  function 0			    |
| Vendor:          8086  Intel Corporation		    |
| Device:          122E  82371FB: PCI to ISA bridge	    |
| Revision:        2					    |
| Class:           6.1					    |
| Header type:     Multi-function			    |
| PCI IRQ:         A:disabled  B:11  C:disabled  D:disabled |
| MB IRQ:          A:15  B:7				    |
| PS2 Mouse IRQ12: Disable				    |
| Level mode IRQs: 11					    |
| 8 bt I/O rcvry:  6.5 {3.5-11.5}			    |
| 16 bt I/O rcvry: 5.5 {3.5-7.5}			    |
-------------------------------------------------------------

   In some cases, I listed the set of possible values in addition to
showing the current value.  When I did so, I always enclosed the
possible values in {}.

   I initially wrote PCI.EXE to check on and override the IRQ
assignments made by the PnP sections of a few BIOS's that didn't give
the user enough control over IRQ's.  In the above example, the BIOS
reserved IRQ 11 for the display controller.  Even though the display
driver could never use an IRQ, the BIOS gave me no choice to disable it.
(I could switch it to another IRQ, but not eliminate it).  Similarly
this BIOS unconditionally assigned IRQ's to devices built into the
motherboard.  It assigned IRQ 15 to the second IDE port (even though
nothing was connected to it), and assigned IRQ 7 to the printer port.

   In order to have more IRQ's available for ISA devices, I added the
following command to my AUTOEXEC.BAT:

PCI IMA- IPB-

   That disabled the IRQ for Mother board device A and for PCI device B.
Then I could use IRQ's 11 and 15 for ISA devices.

   Note that I am not sure my program correctly reports or changes the
assignment of IRQ 12 to the PS2 mouse port.  I have gotten inconsistent
results, and on most motherboards cannot use IRQ 12 for an ISA device
regardless of how it is set by either PCI.EXE or the BIOS.

---------------------------------------------------------------------------
| PCI bus: 0  device: 00  function: 0                                     |
| Vendor:          1039  Silicon Integrated System			  |
| Device:          5571  						  |
| Fast Back-to-Back:        Disabled					  |
| SRAM:                     3-1-1-1-1-1-1-1				  |
| Write Merge:              Disabled					  |
| L2 Cache:                 Enabled  512K  Write-back  Linear mode	  |
| L1 Cache:                 Enabled					  |
| DRAM leadoff:             5 {4-5}					  |
| Page miss after fetch:    Disabled					  |
| Page miss after read:     Enabled					  |
| Page miss after write:    Enabled					  |
| Refresh cycle time:       15.6 {15.6 62.4 124.8 187.2}		  |
| FP/EDO Refresh RAS pulse: 6 {3-6}					  |
| FP/EDO RAS precharge:     4 {2-4}					  |
| FP/EDO RAS to CAS delay:  4 {2-4}					  |
| FP CAS low width:         2 {1-2}					  |
| EDO CAS low width:        1 {1-2}					  |
| EDO Back-to-Back:         3 {2-3}					  |
| RAMW# assertion:          Normal					  |
| MDLE delay:               7 {0-15}					  |
| SDRAM CAS latency:        3 {2-3}					  |
| SDRAM Write retire:       X-2-2-2					  |
| CAS# Delay:               0 {0-15}					  |
| Current rating:           RAS:16 CAS:8 MA:16,16,16 RAMW:8,8 AD:8 Misc:8 |
| RAM Voltage:              3.3						  |
| RAM Bank 0:               8 Mb  (type 0x04)				  |
| RAM Bank 1:               8 Mb  (type 0x18)				  |
---------------------------------------------------------------------------

   In the above example, I was trying to use an SDRAM DIMM in a Mustang
R534 motherboard.  The RAM vendor said the SDRAM was 7 ns.  I think he
was mistaken.  The SDRAM worked at 66Mhz, but not at 75Mhz (60 ns EDO
worked in the same system up to 83Mhz).

   I didn't find documentation on the SIS registers 60 to 6B, which
control the size and type of the RAM banks.  The size part was obvious,
but I have no idea how the types are encoded.  EDO was always type 0 and
SDRAM (as shown) was type 0x04 for even banks and type 0x18 for odd
banks.  Each 16Mb DIMM was seen as two 8Mb banks.

   If you have any better info on the above question, or better names or
explainations for things like "MDLE", please EMAIL me.

---------------------------------------------------------------------------
| PCI bus: 0  device: 00  function: 0					  |
| Vendor:          8086  Intel Corporation				  |
| Device:          1250  82439HX: System controller			  |
| Revision:        1							  |
| Class:           6.0							  |
| L2 Cache:        Pipelined Burst 256Kb (64Mb limit)			  |
| Drive Strength:  MA[0:1] = 12 mA,  MA[2:11] = 12 mA			  |
| Refrsh based on: 60 MHz						  |
| Start DRAM read: One cycle early					  |
| DRAM timing:     Read:7333, EDO read:7222, Write:6222, RAS/CAS:2, Pre:3 |
|                  {6333-7444} {6222-7444}   {5222-6444}   {2-3}    {3-4} |
| C0000-C7FFF:     Read Cache						  |
| C8000-EFFFF:    							  |
| F0000-FFFFF:     Read Cache						  |
| Bank 0:          32Mb EDO						  |
| SMM:             Enabled						  |
---------------------------------------------------------------------------

   On my own system, the BIOS only has selections for 60ns RAM or 70 ns
RAM.  It doesn't let you set individual DRAM timing options.  Since I
have tested (in a different system) that my 60 ns SIMMs are reliable at
far faster than the standard settings for 60 ns, I wanted to set the
DRAM timing to the fastest that the HX chipset supports (which is one
cycle per burst faster than my BIOS was setting).  I added the following
to my AUTOEXEC.BAT:

PCI R58=55

   As expected, CTCM reported that my main memory was then 7% faster.
WARNING:  That command only has that result with the 82439HX chip.  You
need to consult chipset documentation to construct similar commands for
other chips.

READING / WRITING  PCI  REGISTERS  IN  HEXIDECIMAL
--------------------------------------------------

pci rREG,DEV,FNC,BUS?CNT

   The above command will display CNT registers starting at register REG
in function FNC of device DEV on bus BUS.  If you leave out BUS, FNC,
etc., they will default to zero.  If you leave out CNT, it will default
to 1.  For example,

pci r4C,7?

   The above will display register 4C from device 7.

pci r60?8

   The above will display registers 60 through 67 of device 0.

pci rREG,DEV,FNC,BUS=VAL

   The above command sets a register to the specified value.

OTHER  COMMANDS
---------------

pci 6     Displays some information from Cyrix 6x86 registers.  Not
          really associated with PCI configuration.

pci ilNN+  Changes the IRQ number NN to or from level mode.  With some
pci ilNN-  devices, IRQ sharing is made easier by setting the IRQ to
           level mode.

pci imm+  Enables or disable the reservation of IRQ 12 for the
pci imm-  motherboard mouse.  This feature hasn't produced the expected
          results in most cases, so there is probably some detail I
          don't understand yet.

pci imX=NN  Sets motherboard device X to use IRQ NN.

pci imX-    Sets motherboard device X to use no IRQ.

pci ipX=NN  Sets PCI device X to use IRQ NN.

pci ipX-    Sets PCI device X to use no IRQ.


PLEASE  READ  THIS
------------------

   Use this program entirely at your own risk.  I make no claim that
this program is suitable or safe for any purpose.

   If you do find errors in the program, please notify me, but I
cannot make any promises about whether or when I might fix them.
